A Literature Review on Piezo-MEMS for Ultrasonic Through-Metal Communication and Power Transfer
16.09.2025
Implementation of an AI-Assisted CI/CD Pipeline for KiCad Library Quality Assurance
15.09.2025
Semi-Automated Analog Layout Generation Using Cadence SKILL and Parameterized Cells (PCells)
30.07.2025
Masterarbeit
Custom analog layout is traditionally a manual process requiring skilled designers to ensure matching, symmetry, and layout efficiency. This work proposes a semi-automated layout generation flow leveraging the Cadence Virtuoso Design Environment with SKILL scripting and PCells (Parameterized Cells). The proposed method aims to speed up layout generation while maintaining high design quality and layout compliance.
Betreuer/in: Ashwin George, M.Sc.
Adapting the HDL lab to a Digital-On-Top Design Flow
13.06.2025
Developing a Minor Embedding Algorithm for Oscillator based Ising Machines using Reinforcement Learning
06.05.2025
Bachelorarbeit, Masterarbeit, Projektseminar
Betreuer/in: Maximilian Naneder, M.Sc.
Master Thesis: Short-Channel Multi-Decade Exponentiator and Logarithmizer in 28nm technology
Kurzkanal- Exponenzierer und Logarithmierer für mehrere Dekaden in 28nm-Technologie
10.09.2024
Modellierung und Kompensation der Drift von integrierten Temperatur- und Luftfeuchtigkeitssensoren
28.08.2024
Masterarbeit
Untersuche und analysiere die Drift von Temperatur- und Feuchtigkeitssensoren unter extremen Umgebungsbedingungen zur Verbesserung der Sensorgenauigkeit.
Betreuer/in: Prof. Dr.-Ing. Ferdinand Keil
OpenCL implementation of ’Volterra’ system models for GPU-accelerated computation
03.05.2023