Construction and Simulation of an In-Memory Capable CMOS SRAM Array Enabling AND and OR Operations while Maintaining Low Area Overhead
2025/06/13
Master thesis
Adapting the HDL lab to a Digital-On-Top Design Flow
2025/06/13
Developing a Minor Embedding Algorithm for Oscillator based Ising Machines using Reinforcement Learning
2025/05/06
Bachelor thesis, Master thesis, Projectseminar
Supervisor: Maximilian Naneder, M.Sc.
Master Thesis: Short-Channel Multi-Decade Exponentiator and Logarithmizer in 28nm technology
Kurzkanal- Exponenzierer und Logarithmierer für mehrere Dekaden in 28nm-Technologie
2024/09/10
Modellierung und Kompensation der Drift von integrierten Temperatur- und Luftfeuchtigkeitssensoren
2024/08/28
OpenCL implementation of ’Volterra’ system models for GPU-accelerated computation
2023/05/03