In hardware for AI group, we are working on converting neural networks into logic flows for efficient execution of neural networks on CPUs. In this project, we need to evaluate how certain design changes of a neural network affect the latency and power performance during inference on RISC-V CPUs. Currently this is done using simulators. Moving forward we want to measure on FPGAs, which is the purpose of this project seminar.

The goal of this project seminar is to synthesize an existing RISC-V CPU onto an FPGA Boards using Chipyard [0]. This will then be used to run a neural network of the MLPerf tiny benchmark suite [1]. Ideally, if there is enough time, the energyrunner [2] will also be integrated to allow for energy measurements for each inference of the network.