Content
| Students elaborate on a research-oriented subject in the area of hardware for neural networks. They submit a written documentation and give a presentation of the acquired advanced knowledge. They provide a set of alternative solutions to a given problem. |
Organization
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Project seminars do not require presence at the university and can be started at any time. If you are interested, please contact the PhD student responsible for your chosen topic to check whether there is a suitable project for you. All further information will be provided via e‑mail. The following open theses are also suitable for a project seminar: |
Dynamic Neural Networks with Early‑Exit Mechanisms
2025/04/20
Implementation a CNN Layer on FPGA
2025/04/20
Latency and Power Measurements of Neural Networks on FPGA-based RISC-V CPUs
2025/04/20
In hardware for AI group, we are working on converting neural networks into logic flows for efficient execution of neural networks on CPUs. In this project, we need to evaluate how certain design changes of a neural network affect the latency and power performance during inference on RISC-V CPUs. Currently this is done using simulators. Moving forward we want to measure on FPGAs, which is the purpose of this project seminar.
The goal of this project seminar is to synthesize an existing RISC-V CPU onto an FPGA Boards using Chipyard [0]. This will then be used to run a neural network of the MLPerf tiny benchmark suite [1]. Ideally, if there is enough time, the energyrunner [2] will also be integrated to allow for energy measurements for each inference of the network.
Prerequisites
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