Geometry/Topology Optimization in High End Lithography


This research project is planned in cooperation with Carl Zeiss SMT GmbH, the Semiconductor Manufacturing Technology business group of ZEISS. Nowadays, most high-end microchips are produced using EUV-Lithography, where a design from a photomask is repeatedly printed on a wafer. Due to the electrodynamic light matter interaction, the photomask design and the corresponding image on the wafer may differ significantly. The goal of this thesis is the formulation, development, and benchmarking of a top-notch topology optimization solution solving inverse problems.